VLSI -(Logic Designing and physical Designing – Front-end + Back-end)



Framing Verilog Concepts,The Design Abstraction Hierarchy, Types of Simulation, Types of Languages, Simulation versus Programming,HDL Learning Paradigms, Where To Get More Information, Reference, Manuals,Usenet


Identifiers,Escaped Identifiers,White Space,Comments,Numbers,Text Macros,Modules,Semicolons,Value Set,Strengths,Numbers, Values, and Unknowns


Primitives,Ports,Ports in Primitives,Ports in Modules,Instances,Hierarchy,Hierarchical Names,Connect by Name,Top-Level Modules,Your First Simulations,Exercise 1 The Hello Simulation,Exercise 2 The 8-Bit Hierarchical Adder


Starting Places for Blocks of Procedural Code,The initial Keyword,The always Keyword,Delays,begin-end Blocks,fork-join Blocks,
Summary of Procedural Timing


What is a System Task?,$display and Its Relatives,Other Commands to Print Results,Writing to Files,Advanced File IO Functions,Setting the Default Radix,Special Characters,The Current Simulation Time,Suppressing Spaces in Your Output,Periodic Printouts,When to Printout Results,A Final System Task,Exercise 3 Printing Out Results from Wires Buried in the Hierarchy


Data Objects in Verilog,Nets,Ranges,Implicit Nets,Ports,Regs,Memories,Initial Value of Regs,Integers and Reals,Time and Realtime,Parameters,Events,Strings,Multi-Dimensional Arrays
Accessing Words and Bits of Multi-Dimensional Arrays,Ports and Regs


Procedural Assignments, Ports and Regs,Best Practices with Procedural Assignments,Procedural Assignment for Combinatorial Logic,Procedural Assignment for Sequential Logic,Philosophy of Intra-Assignment Delays for Sequential Assignments,Conventions Moving Forward


Binary Operators,Unary Operators,Reduction Operators,Ternary Operator,Equality Operators,Concatenations,Logical Versus Bit-Wise Operations,Operations That Are Not Legal On Reals,Working With Strings,Combining Operators,Sizing Expressions,Signed Operations,Signed Constants


Continuous Assignment,Event Control,The always Block for Combinatorial Logic,Event Control Explained,Summary of Procedural Timing


The if Statement,The case Statement,Loops,The forever Loop,The repeat Loop,The while Loop,The for Loop,Exercise 4 Using Expressions and case.


Tasks,Automatic Tasks,Common Uses for Tasks,Functions,Functions and Integers,Automatic Functions,Exercise 5 Functions and Continuous Assignments.


Using The Event Data Type,Procedural Continuous Assignments,A Reminder About Ports and Regs,Modeling with Inout Ports,Named Blocks, The Disable Statement,When is a Simulation Done?


Combinatorial Udps,Optimistic Mux,Pessimistic Mux,The Gritty Details,Sequential UDPS,UDP Instances,The Final Details,Exercise 6 Using UDPs.


N-Bit Mux,N-Bit Adder,N By M Mux,N By M Ram,Using Parameterized Modules,Parameter Passing by Name,Parameter Passing by Order,Parameter Passing by Named List,Values of Parameters in Module Instances.


State Machine Types,State Machine Modeling Style,State Encoding Methods,Default Conditions, Implicit State Machines,Registered And Unregistered Outputs,Factors in Choosing a State Machine Modeling Style,


Modeling Combinatorial Logic,Combinatorial Models Using Continuous Assignments,Combinatorial Models Using the always Block and regs,Combinatorial Models Using Functions, Modeling Sequential Logic,Sequential Models Using always,Sequential Models Using initial,Sequential Models Using Tasks, Modeling Asynchronous Circuits, Modeling a One-Shot, Modeling Asynchronous Systems, Special-Purpose Models,Two-Dimensional Arrays, Z-Detectors,Multiplier Examples,A Proven, Successful Approach to Modeling.


Forces That Influence Modeling Style,Evolution of a Model,Modeling Style and Synthesis,Is It Synthesizable?,Learning From Other People’s Mistakes,When To Use Udps,Blocking and Non-Blocking Assignments,


Introduction to Testing,MANAGEMENT,Model Size versus Test Volume,Types of Tests,Functional Testing,Regression Testing,Sign-Off,System Test versus Unit Tests,Creating Test Plans,The Basic Test Cycle,Hardware Setup and Hold and Response Time,The Test Cycle for Combinatorial Models,The Test Cycle for Sequential Models,Self-Checking Test Benches,Response-Driven Stimulus,Test Benches for Inouts,Loading Files into Verilog Memories,Test Benches with No Test Vectors,Using A Script To Run Test Cases,Modeling Bist,The Surround and Capture Method.


File Organization,Declaration Organization,ANSI Style ports,Testcase Organization,Including Test Cases,Conditionally Running Rests,Model Reuse,Summary of Model Orgainzation Compile Directives,Pre-defined Text Macros.


Mismatched Ports,Missing or Incorrect Declarations,Missing Regs,Missing Widths,Reversed Ranges,Improper Use of Procedural Continuous Assignments,Missing initial or always Blocks,Zero-Delay always Loops,initial Instead of always,Missing Initialization,Overly Complex Code,Unintended Storage,Timing Errors,Negative Setup Time,Zero-Delay Races,Tool Specific Pragmas.


Overview of Functional Debugging,Where Are the Errors?, Universal Techniques,Printing Out Messages,“I am here.”,Values,The Log File,Using Waveforms,Interactive Debugging,Going Interactive,The Prompts,Special Keys in Interactive Mode,Command History,The Key File,Traversing and Observing,Back-Tracing Fan-In,Using force and release.Waveforms, Graphical User Interfaces and Other Conveniences, Catching Problems Later in a Simulation,Isolating Differences in Models, Summary of Debugging.


Code Coverage and Test Plans,Code Coverage and Fifos,Code Coverage and State Machines,Code Coverage and Modeling Style,

 Module 2


>>           Gate-level combinational circuit

  • Introduction
  • General description
  • Basic lexical elements and data types -Lexical elements
  • Data types – Four-value system, Data type groups, Number representation, Operators
  • Program skeleton – Port declaration, Program body, Signal declaration, Another example
  • Structural description
  • Testbench
  • Suggested experiments – Code for gate-level greater-than circuit; Code for gate-level binary decoder

>>           Overview of FPGA and EDA software

  • Introduction FPGA – Overview of a general FPGA device; Overview of the Xilinx Spartan3 devices
  • Development flow
  • Overview of the Xilinx ISE project navigator
  • Short tutorial on ISE project navigator- Create the design project and HDL codes,
  • Create a testbench and perform the RTL simulation, Add a constraint file and synthesize and implement the code,
  • Generate and download the configuration file to an FPGA device
  • Short tutorial on the ModelSim HDL simulator
  • Suggested experiments – Gate-level greater-than circuit, Gate-level binary decoder

>>           RT-level combinational circuit

  • Introduction
  • Operators – Arithmetic operators, Shifi operators, Relational and equality operators
  • Bitwise, reduction, and logical operators, Concatenation and replication operators, Conditional operators
  • Operator precedence, Expression bit-length adjustment, Synthesis of z and x values
  • Always block for a combinational circuit- Basic syntax and behavior, Procedural assignment, Variable data types, Simple examples
  • If statement- Syntax, Examples
  • Case statement- Syntax, Examples, The case z and case x statements, The full case and parallel case
  • Routing structure of conditional control constructs- Priority routing network, Multiplexing network
  • General coding guidelines for an always block – Common errors in combinational circuit codes, Guidelines
  • Parameter and constant- Constant, Parameter, Use of parameters in Verilog
  • Design examples – Hexadecimal digit to seven-segment LED decoder, Sign-magnitude adder, Barrel shifter, Simplified floating-point adder
  • Suggested experiments -Multifunction barrel shifter, Dual-priority encoder, BCD incrementor, Floating-point greater-than circuit, Floating-point and signed integer conversion circuit, Enhanced floating-point adder

>>           Regular Sequential Circuit

  • Introduction – D FF and register, Synchronous system, Code development
  • HDL code of the FF and register, D FF, Register, Register file, Storage components in a Spartan-3, Device – Xilinx Specific
  • Simple design examples, Shift register, Binary counter and variant
  • Testbench for sequential circuits
  • Case study- LED time-multiplexing circuit, Stopwatch, FIFO buffer
  • Suggested experiments – Programmable square-wave generator, PWM and LED dimmer, Rotating square circuit, Heartbeat circuit, Rotating LED banner circuit, Enhanced stopwatch, Stack

>>           FSM

  • Introduction, Mealy and Moore outputs, FSM representation
  • FSM code development
  • Design examples – Rising-edge detector, Debouncing circuit, Testing circuit
  • Suggested experiments – Dual-edge detector, Alternative debouncing circuit, Parking lot occupancy counter


>>           FSMD

  • Introduction- Single RT operation, ASMD chart, Decision box with a register
  • Code development of an FSMD- Debouncing circuit based on RT methodology, Code with explicit data path components, Code with implicit data path components, Comparison, Testing circuit
  • Design examples- Fibonacci number circuit, Division circuit, Binary-to-BCD conversion circuit, Period counter, Accurate low-frequency counter
  • Suggested experiments – Alternative debouncing circuit, BCD-to-binary conversion circuit, Fibonacci circuit with BCD I/O: design approach 1, Fibonacci circuit with BCD I/O: design approach 2, Auto-scaled low-frequency counter, Reaction timer, Babbage difference engine emulation circuit

>>           Selected Topics of Verilog

  • Blocking versus non blocking assignment – Overview, Combinational circuit, Memory element, Sequential circuit with mixed blocking and non blocking, Assignments, Sequential circuit with mixed blocking and non blocking assignments
  • Alternative coding style for sequential circuit – Binary counter, FSM, FSMD
  • Use of the signed data type
  • Use of function in synthesis
  • Additional constructs for test bench development – Always block and initial block, Procedural statements, Timing control, Delay control, Event control, Wait statement, Timescale directive, System functions and tasks, User-defined functions and tasks, Example of a comprehensive test bench
  • Suggested experiments – Shift register with blocking and non blocking assignments, Alternative coding style for BCD counter, Alternative coding style for FIFO buffer, Alternative coding style for Fibonacci circuit, Dual-mode comparator, Enhanced binary counter monitor, Test bench for FIFO buffer




>>           UART

  • Introduction
  • UART receiving subsystem – Oversampling procedure, Baud rate generator, UART receiver, Interface circuit
  • UART transmitting subsystem
  • Overall UART system – Complete UART core, UART verification configuration
  • Customizing a UART
  • Suggested experiments – Full-featured UART, UART with an automatic baud rate detection circuit, UART with an automatic baud rate and parity detection circuit, UART-controlled stopwatch, UART-controlled rotating LED banner

>>           PS2 Keyboard

  • Introduction
  • PS2 receiving subsystem – Physical interface of a PS2 port, Device-to-host communication protocol, Design and code
  • PS2 keyboard scan code – Overview of the scan code, Scan code monitor circuit
  • PS2 keyboard interface circuit – Basic design and HDL code, Verification circuit
  • Suggested experiments – Alternative keyboard interface I, Alternative keyboard interface II, PS2 receiving subsystem with watchdog timer, Keyboard-controlled stopwatch, Keyboard-controlled rotating LED banner

>>           PS2 Mouse

  • Introduction
  • PS2 mouse protocol – Basic operation, Basic initialization procedure
  • PS2 transmitting subsystem – Host-to-PS2-device communication protocol, Design and code
  • Bidirectional PS2 interface – Basic design and code, Verification circuit,
  • PS2 mouse interface -Basic design, Testing circuit
  • Suggested experiments -Keyboard control circuit, Enhanced mouse interface, Mouse-controlled seven-segment LED display

>>           External SRAM

  • Introduction
  • Specification of the IS6 1 LV25616AL SRAM – Block diagram and 110 signals, Timing parameters
  • Basic memory controller – Block diagram, Timing requirement, Register file versus SRAM
  • A safe design -ASMD chart, Timing analysis, HDL implementation, Basic testing circuit, Comprehensive SRAM testing circuit
  • More aggressive design -Timing issues, Alternative design I, Alternative design II, Alternative design III, Advanced FPGA features xi1inx specific
  • Suggested experiments – Memory with a 5 12K-by- 16 configuration, Memory with a 1M-by-8 configuration, Memory with an 8M-by-1 configuration, Expanded memory testing circuit, Memory controller and testing circuit for alternative design I, Memory controller and testing circuit for alternative design II, Memory controller and testing circuit for alternative design III, Memory controller with DCM, High-performance memory controller

>>           Xilinx Spartan3 Specific Memory

  • Introduction
  • Embedded memory of Spartan-3 device – Overview, Comparison
  • Method to incorporate memory modules -Memory module via HDL component instantiation, Memory module via Core Generator, Memory module via HDL inference
  • HDL templates for memory inference – Single-port RAM, Dual-port RAM, ROM
  • Suggested experiments – Block-RAM-based FIFO, Block-RAM-based stack, ROM-based sign-magnitude adder, ROM-based sin(x)function, ROM-based sin(x) and cos(x) functions

>>           VGA controller I: graphic

  • Introduction
  • Basic operation of a CRT – VGA port of the S3 board, Video controller,
  • VGA synchronization -Horizontal synchronization, Vertical synchronization, Timing calculation of VGA synchronization signals, HDL implementation, Testing circuit
  • Overview of the pixel generation circuit
  • Graphic generation with an object-mapped scheme – Rectangular objects, Non-rectangular object, Animated object
  • Graphic generation with a bit-mapped scheme – Dual-port, RAM implementation, Single-port RAM implementation
  • Suggested experiments – VGA test pattern generator, SVGA mode synchronization circuit, Visible screen adjustment circuit, Ball-in-a-box circuit, Two-balls-in-a-box circuit – 6 Two-player pong game, Breakout game, Full-screen dot trace, Mouse pointer circuit, Small-screen mouse scribble circuit, Full-screen mouse scribble circuit

>>           VGA controller II: text

  • Introduction
  • Text generation -Character as a tile, Font ROM, Basic text generation circuit, Font display circuit, Font scaling
  • Full-screen text display
  • The complete pong game – Text subsystem, Modified graphic subsystem, Auxiliary counters, Top-level system
  • Suggested experiments – Rotating banner, Underline for the cursor, Dual-mode text display, Keyboard text entry, UART terminal, Square-wave display, Simple four-trace logic analyzer, Complete two-player pong game, Complete breakout game



>>           PicoBlaze Overview

  • Introduction
  • Customized hardware and customized software – From special-purpose FSMD to general-purpose microcontroller, Application of microcontroller
  • Overview of PicoBlaze -Basic organization,Top-level HDL modules
  • Development flow
  • Instruction set – Programming model, Instruction format, Logical instructions, Arithmetic instructions, Compare and test instructions, Shift and rotate instructions, Data movement instructions, Program flow control instructions, Interrupt related instructions
  • Assembler directives – The KCPSM3 directives, The PBlazeIDE directives


>>           PicoBlaze Assembly Code Development

  • Introduction
  • Useful code segments -KCPSM3 conventions, Bit manipulation, Multiple-byte manipulation, Control structure
  • Subroutine development
  • Program development – Demonstration example, Program documentation
  • Processing of the assembly code – Compiling with KCSPM3, Simulation by PBlazeIDE, Reloading code via the JTAG port, Compiling by PBlazeIDE
  • Syntheses with PicoBlaze
  • Suggested experiments – Signed multiplication, Multi-byte multiplication, Barrel shift function, Reverse function, Binary-to-BCD conversion, BCD-to-binary conversion, Heartbeat circuit, Rotating LED circuit, Discrete LED dimmer

>>           PicoBlaze 110 Interface

  • Introduction
  • Output port – Output instruction and timing, Output interface
  • Input port – Input instruction and timing, Input interface
  • Square program with a switch and seven-segment LED display interface – Output interface, Input interface, Assembly code development, HDL code development
  • Square program with a combinational multiplier and UART console -Multiplier interface, UART interface, Assembly code development, HDL code development
  • Suggested experiments – Low-frequency counter I, Low-frequency counter II, Auto-scaled low-frequency counter, Basic reaction timer with a software timer, Basic reaction timer with a hardware timer, Enhanced reaction timer, Small-screen mouse scribble circuit, Full-screen mouse scribble circuit, Enhanced rotating banner, Pong game, Text editor

>>           PicoBlaze Interrupt Interface

  • Introduction
  • Interrupt handling in PicoBlaze  – Software processing, Timing, External interface, Single interrupt request, Multiple interrupt requests
  • Software development considerations – Interrupt as an alternative scheduling scheme, Development of an interrupt service routine
  • Design example – Interrupt interface, Interrupt service routine development, Assembly code development, HDL code development, Suggested experiments – Alternative timer interrupt service routine, Programmable timer, Set-button interrupt service routine, Interrupt interface with two requests, Four-request interrupt controller.


Introduction Technology scale down Frequency Improvement Increased layers

Reduced power supply

The MOS device

The MOS Logic simulation of the MOS MOS layout

Vertical aspect of the MOS

Static MOS characteristics Dynamic MOS behavior Analog simulation

Mos options

Transmission gate: the perfect switch

Layout considerations

 MOS modeling

The MOS model 1

The MOS model 3

The model BSIM4

Temperature effects on the MOS High frequency behavior of the MOS

The Inverter

The logic Inverter

The CMOS inverter (Power, supply, frequency) Layout design (plasma, latchup)

Simulation of the inverter Views of the process Buffer

3-state inverter

Analog behavior of the inverter

Ring oscillator

Temperature effects

Interconnects Signal propagation Capacitance load Resistance effect Inductance effect Buffers

Clock tree

Supply routing

 Basic Gates


From boolean expression to layout NAND gate (micron, sub-micron) OR3 gate


Complex gates

Multiplexors (Mux-demux) Pulse generator


Data formats: unsigned, signed fixed

Half adder gate

Full adder gate

4-bit adder Comparator Multiplier ALU

Low power arithmetics


Latches RS latch D-Latch

Edge-trigged latch

Latch optimization (conso, speed, fanout) Counter

Project: programmable pulse generator



Mux for FPGA Configurable logic block Look-up table Interconnection

Programmable Interconnection Points

Propagation delay


The world of Memories

Static RAM memory (4T, 6T) Decoder (low power) Dynamic RAM memory Embedded RAM

Sense ampli

ROM memory EEPROM memory FRAM memory

Analog Cells

Diode connected MOS Voltage reference Current Mirror Amplifiers (Class) Voltage regulator

Wide range amplifier

Charge pump


RF Analog Cells Osc illators Inductors

Sample & Hold


Voltage-controlled Oscillators

PLL project

Power amplifiers

Converters Introduction Converter parameters Sample hold


Input/Output Interfacing

Level shifter

Pad stucture

Input pad (schmidt, protect, buffer) Output pad (log, analog, multi drive) Pad ring

Packages IBIS LVDS

High performance Ios


Layout improvements

2D aspects SOI model Simulation Issues

Future & Conclusion


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